Technical Overview

With a modular book design, the z9 EC Model S54 is designed to provide up to 95% more total system capacity than the z990 Model D32, and has up to double the available memory. The z9 EC now offers the IBM z9 Integrated Information Processor (zIIP), 24 sub capacity settings, the FICON Express4 with 1, 2, or 4 Gbps, and up to 336 FICON Express2 or FICON Express4 channels.

The Modified Indirect Data Address Word (MIDAW) facility is designed to improve FICON(R) performance. The number of FICON Express2 and FICON Express4 open exchanges (concurrent I/O operations) that may be active simultaneously has been increased from 32 to 64 per FICON channel.

The z9 EC is focused on providing higher availability and reducing planned and unplanned outages — which, when properly configured, may be accomplished with improved nondisruptive replace, repair, and upgrade functions for memory, books, and I/O as well as extending nondisruptive capability to download Licensed Internal Code updates.

Integrated clear key encryption security-rich features on the z9 EC include support for Advanced Encryption Standard, Secure Hash Algorithm-256, remote key load of ATMs and POS and integrated Pseudo Random Number Generation. These functions are designed to improve performance and cost management.

Application of the z9 EC advanced virtualization technologies creates a solid foundation for flexible integration of business and information management.

Innovations on the z9 EC can help to ensure you have a security-rich platform, can help maximize your resources and their utilization, and can help provide you the ability to integrate applications and data across the infrastructure. The z9 EC is designed to be a flagship component of your heterogeneous environment.

The z9 EC continues the evolution of the mainframe, building upon the structure introduced on z990 in support of z/Architecture(TM), reliability, availability, scalability, and clustering. The z9 EC expands upon a key attribute of the platform – availability – to help ensure you have a resilient infrastructure designed to satisfy the requirements of On Demand Business. With the increased performance and total system capacity possible for the z9 EC, you have an opportunity to continue to consolidate diverse applications on a single platform.

IBM continues the 40 year evolution of the mainframe by providing you with the ability to choose the optimum server size and resources, utilize improvements in link data rates, integrate additional cryptographic function and allow the mixing of OSA Layer2 and Layer3 traffic.

The z9 EC is designed to provide:

• Nearly double the total system capacity of z990
• Uniprocessor performance improvement designed to be up to 35% (based on LSPR mixed workload average)
• Up to 54 Processor Units (PUs) compared to a maximum of 32 PUs on z990
• IBM System z9 Integrated Information Processor
• 24 New Subcapacity Settings
• Conversions of CPs, IFLs, zIIPs or ICFs to and from zAAPs
• Capacity Backup for zAAP, IFL, zIIP and ICF
• Double the available memory per model – up to 128 GB per book
• Increased host bus bandwidth between memory and I/O
• Up to 16 Self-Timed Interconnects (STIs) per book, 2.7 GB each for I/O, a 35% increase in STI speed compared to z990s 2.0 GB STI bus
• FICON Express4 supporting 4 Gbps link data rate with:
  • Connectivity to existing and future 1, 2, and 4 Gbps servers, switches, directors, and devices (disk, tape, printers)
  • Improved performance
  • Enhanced availability with Small Form Factor Pluggable (SFP) optics
  • Support of two unrepeated distance options (4 kilometer and 10 kilometer) when using LX transceivers with single mode fiber optic cabling
• Modified Indirect Data Address Word facility
• Two subchannel sets per LCSS
• Multiple Subchannel Sets (MSS) which is designed to allow improved device connectivity for Parallel Access Volumes (PAVs)
• Improved performance over native FICON channels for programs that process data sets exploiting striping and compression (such as DB2, VSAM, PDSE, HFS, and zFS) by reducing channel, director, and control unit overhead when using the Modified Indirect Data Address Word (MIDAW) facility
• Increased connectivity for Crypto, FICON, and OSA in one I/O cage
• Increased number of open exchanges (concurrent I/O operations) that may be active simultaneously for FICON Express2, from 32 to 64 per channel
• Up to 336 FICON Express channels, a 40% increase compared to z990
• Availability enhancements for FICON
• Increased number of open exchanges (concurrent I/O operations)
• N_Port ID Virtualization
• Improved availability with:
  • Enhanced book availability
  • Redundant I/O interconnect
  • Enhanced driver maintenance
  • Dynamic oscillator switch over
  • Program directed re-IPL
  • Concurrent MBA fanout card hot-plug
• Support of up to 60 LPARs
• CPACF enhancements – AES, PRNG, SHA-256
• Configurable Crypto Express2
• Integration of New Crypto functions such as:
  • Remote Keyload for ATMs
  • Implementation of ISO 16609 CBC Mode TDES for MAC
• OSA/SF enhancements to facilitate management of IP and MAC addresses
• OSA Layer 2/Layer 3 transport enhancement
• HiperSockets** support of IPv6
• OSA-Express2 1000BASE-T Ethernet
• OSA-Express2 OSN (OSA for NCP)
• Additional LAN connectivity option with introduction of OSA-Express2 1000BASE-T Ethernet
• OSA-Express2 OSN (OSA for NCP), providing Channel Data Link Control (CDLC) protocol support on the z9 EC for the IBM Communication Controller for Linux on zSeries** (CCL) allowing system administrators to configure, manage, and operate their CCL Network Control Programs (NCPs) in the same manner as their ESCON-attached 374x NCPs
• GDPS enhancements – to improve performance and availability

z9 EC Chip Details

All chips use CMOS 10S chip technology, except for the clock chip (CMOS 8S). CMOS 10S is state-of-the-art microprocessor technology based on ten-layer Copper Interconnections and Silicon-On Insulator technologies. The chip lithography line width is 0.125 micron.

The eight PU chips come in two versions. For the z9 EC models S08, S18, S28, and S38, the Processor Units (PUs) on the MCM in each book are implemented with a mix of single-core and dual-core PU chips. Four single-core and four dual-core chips are used, resulting in 12 PUs per MCM.

For the z9 EC Model S54, the Processor Units (PUs) on the MCMs in all books are implemented with eight dual-core PU chips, resulting in 16 PUs per MCM.

Eight to ten PUs of the 12 PU version may be characterized for customer use. The two standard SAPs are initially allocated to the dual-core processor chips. Optionally, up to two spare chips may be allocated on an MCM. System-wide, two spare chips are available that may be allocated on any MCM of the system. Each core on the chip runs at a cycle time of 0.58 nanoseconds. Each dual-core PU chip measures 15.78 x 11.84 mm and has 121 million transistors.

In the 16 PU version, used in all MCMs of a z9 EC Model S54, 12 to 14 PUs are available for customer use. Optionally, up to two spare chips may be allocated on an MCM. System-wide, two spare chips are available that may be allocated on any MCM of the system. Each PU has a 512 KB on chip Level 1 cache (L1) that is split into a 256 KB L1 cache for instructions and a 256 KB L1 cache for data, providing large bandwidth.

Inside the IBM z9 EC 204