Technical Overview

The 3907-ZR1 supports 64 to 8000 GB of memory, from 1 to 6 central processors, 3o total configurable cores, and up to 8 PCIe+ fanouts. The PCIe+ I/O drawers house up to 64 I/O cards in support of cryptography (Crypto Express6S), the storage area network (FICON Express16S+ and IBM zHyperLink Express), the Ethernet local area network (OSA-Express6S and 10GbE RoCE Express2), Coupling Express LR, and compression (zEDC Express).

The newest member of the IBM z14 product portfolio, the new z14 Model ZR1 delivers high-reliability, high-speed functions in a smaller, industry-standard frame, that easily partners with other platforms in a cloud data center. As part of the IBM Z portfolio, the z14 Model ZR1 provides a highly available platform that delivers differentiated value, designed to enable business growth, reduce cost, and protect existing investments.

High-performance encryption for a pervasive encryption strategy

• IBM Z processor-based cryptography with the Central Processor Assist for Cryptographic Functions (CPACF).
• z/OS data set encryption and z/OS Coupling Facility encryption to help create an envelope of protection.
• Support for dm-crypt on Linux on Z transparent file and volume encryption using industry-unique CPACF protected keys.
• Trusted Key Entry (TKE) 9.0 Licensed Internal Code (LIC).
• Cryptographic performance with the Crypto Express6S (#0893).
• IBM Secure Service Containers, soon to be enhanced via integration with IBM Cloud Private, designed such that IBM, client, or third-party Docker and Kubernetes based applications can be securely deployed and encrypted in their own partitions without application changes.

Speed and scalability

• Economies of scale with next-generation simultaneous multithreading (SMT) for Linux and zIIP eligible workloads, new support for the I/O System Assist Processor (SAP), 2x AES performance over z13s, a True Random Number Generator with CPACF support, SHA3 support, and RSA/ECC acceleration.
• Java8 SR5 performance support via Guarded Storage Facility with z/OS for reducing program pauses during Java garbage collection.
• New instructions in Single Instruction Multiple Data (SIMD) which are designed to give a performance boost for both traditional and new workloads.
• FICON Express16S+ (#0427, 0428) which is designed with a boost in I/O rates and a reduction in single stream latency to help absorb large application and transaction spikes driven by large, unpredictable analytic and mobile workloads.
• Improved compression ratio (using Huffman coding) and order- preserving compression for the on-chip compression coprocessor which results in fewer CPU cycles to enable further compression of data, improving memory, transfer, and disk efficiency.
• 30 cores available for client configuration (versus 20 on z13s), with faster uniprocessor performance as compared to z13s.
• Up to 8 terabytes (TB) of available Redundant Array of Independent Memory (RAIM) real memory per server to help improve transaction response times, lower CPU costs, simplify capacity planning, enlarge in-memory buffer pools, and ease deploying memory-intensive workloads.
• 2x more on-chip cache per core, compared to z13s, to minimize memory waits while maximizing the throughput of concurrent workloads — perfectly optimized for data serving.
• 10 GbE RoCE Express2 with 4x more virtual functions per adapter and a performance improvement.
• Coupling Express LR (#0433), for long reach coupling connectivity, in addition to continued support of Integrated Coupling Adapter Short Reach (ICA-SR) (#0172). These adapters replace older-generation 12x and 1x InfiniBand HCA3-O coupling links.
• IBM Virtual Flash Memory (#0614), the replacement for the Flash Express features (#0402, #0403), offering up to 2.0 TB of virtual flash memory for improved application availability and to handle paging workload spikes.
• IBM zHyperLink Express (#0431), which uses a direct-connect short- distance link (zHyperLink) to deliver low-latency connectivity between z14 and FICON storage systems. Working in conjunction with a corresponding DS8000 Systems Storage zHyperLink feature and an exploiter such as DB2 12 with a PTF, zHyperLink Express delivers the next generation of I/O for IBM Z storage.

Simplified approaches

• IBM Hardware Management Console (HMC) 2.14 with GUI updates to improve workspace and manage system time. New security features include Multifactor Authentication and a new HMC Mobile application for monitor and recover action controls.
• IBM Dynamic Partition Manager enhancements which provide a consumable IBM Z experience, with visual representations of partitions and options for clear understanding of new and existing Linux on IBM Z, and z/VM partitions.
• Optimized z/OS platform for IBM Open Data Analytics for z/OS, and portable analytics, such as IBM DB2 Analytics Accelerator (IDAA), for integrating real-time data intelligence and operational decision making as transactional data is being created.
• Container Pricing for z/OS that allows for development and testing of new workloads to be managed separately from production workload, thereby increasing access and predictability for new deployment activities.
• Ongoing collaboration with a wide network of partners across the ecosystem to take advantage of opportunities like Docker on IBM Z.
• Insight to your full portfolio using Application Discovery and Delivery Intelligence (ADDI) to pinpoint opportunities for efficiency in existing code.

The performance advantage

IBM’s Large Systems Performance Reference (LSPR) method is designed to provide comprehensive z/Architecture processor capacity ratios for different configurations of Central Processors (CPs) across a wide variety of system control programs and workload environments. For ultimate flexibility in capacity, the z/Architecture processor capacity indicator is defined with up to 6 CPs, with 26 segment slices (A-Z notation), where segments run A01 – Z06.

In addition to the general information provided for z/OS 2.3, the LSPR also contains performance relationships for z/VM and Linux operating environments.

The capacity per processor engine of a z14 ZR1 (3907) processor is expected to provide approximately a 10% increase over that of a z13s (2965), with some variation, based on workload and configuration. The IFL and zIIP processors on the z14 ZR1 provide an optional z14 ZR1 multithreading technology capability; with the multithreading function enabled, the performance capacity of an IFL or zIIP is expected to typically be up to 25% higher than without the multithreading function enabled.

The LSPR contains the Internal Throughput Rate Ratios (ITRRs) for z14 ZR1 and the previous-generation IBM Z processor families based upon measurements and projections using standard IBM benchmarks in a controlled environment. The actual throughput that any user may experience will vary depending upon considerations such as the level of multiprogramming in the user’s job stream, the I/O configuration, the workload processed, and the LPAR configuration. Therefore, no assurance can be given that an individual user will achieve throughput improvements equivalent to the performance estimates stated.

Next-generation availability

The z14 processor builds upon the Reliability, Availability and Serviceability (RAS) of the IBM Z family, with the following RAS improvements:

• z14 Level 3 cache enhancements using powerful symbol ECC that now spreads cache data over multiple physical cache arrays. This enables the detection and correction of multibit errors, making the Level 3 cache more resilient and fault tolerant.
• Preemptive DRAM marking added to main memory to isolate and recover failures more quickly.
• Improved small array error handling in the processor cores.
• Additional error thresholding to the processor core to isolate “sick but not dead” failure scenarios.
• An increase in the number of “Resource Groups” (from 2 to 4) to reduce the impact of firmware updates and failures.

z14-ZR1 10-Core Chip Details

The z14 ZR1 PU chip shares the design with the z14 M0x PU chip and is an evolution of the z13s design. It includes the following features:

• CMOS 14nm SOI technology
• Pipeline enhancements, dynamic improved simultaneous multithreading (SMT), enhanced single-instruction multiple-data (SIMD), and redesigned, larger on-chip caches.

Each PU chip includes up to nine active cores (10 cores by design) that run at 4.5 GHz, which means that the cycle time is 0.222 ns. The PU SCMs come in five versions: 5, 6, 7, 8 or 9 active cores.

The PU chip contains the following enhancements:

 

Cache Improvements:
– New power efficient logical directory design
– 33% larger L1 I$ (128 KB), private
– 2x larger L2 D$ (4 MB), private
– 2x larger L3 cache with symbol ECC, shared

Pipeline Optimizations:
– Improved instruction delivery
– Faster branch wake-up
– Reduced execution latency
– Improved Operand store compare (OSC) avoidance
– Optimized second-generation SMT2

Inside the IBM z14-ZR1 3907