Technical Overview

The IBM 2828 is a zEnteprise BC12 (zBC12). With improved processor performance, increased capacity, hybrid computing capabilities, and significant power, space, and cooling benefits, the zBC12 is a perfect fit for infrastructure simplification and cloud computing. The zBC12 is a single frame system with a 4.2 GHz processor frequency and increased cache sizes.

The 2828 zEnterprise family, the IBM zEnterprise BC12 (zBC 12) is designed to help enterprises of all sizes improve customer service by exploiting the latest capabilities of the zEnterprise System. These include an efficient and flexible cloud delivery model, real-time data analytics, and enterprise mobility, all helping you leverage a highly secure and resilient infrastructure.

As an entry point for Enterprise Systems computing, the zBC12 is designed to enable new business capabilities while delivering increased performance and granular growth options in a smaller, more cost-effective footprint.

The zBC12 is also designed to provide continued investment protection to allow you to start small and rapidly expand. You can upgrade from the IBM System z10 Business Class (z10 BC) or the IBM zEnterprise 114 (z114) to the zBC12, as well as from the zBC12 to the IBM zEnterprise EC12 (zEC12) for maximum capacity to support your continued business growth.

Combined with the enhanced IBM zEnterprise BladeCenter Extension (zBX) Model 003 and IBM zEnterprise Unified Resource Manager (zManager), the zBC12 offers a proven hybrid computing design that can help you manage and integrate workloads across multiple architectures (System z, UNIX, and Intel) with the simplicity of a single system.

Inherent in the design of the zBC12:

• A 4.2 GHz processor designed to deliver up to a 36% performance increase per core compared to the z114
• Up to six general purpose processors (CPs) designed to deliver up to 58% more capacity as compared to the z114
• Up to 20% greater granularity with 156 capacity settings on either the Model H06 or Model H13
• Up to 13 Integrated Facility for Linux (IFL) processors to help consolidate up to 62% more work for Linux on System z
• Up to a 2x increase in available memory (496 GB) compared to the z114 for improved performance of memory-demanding workloads such as DB2, IBM WebSphere, and Linux on System z
• Top Exit I/O and power cabling
• Investment protection with upgrade paths from the z10 BC and z114 to the zBC12

Features and functions:

• Capacity limit enforcement with an LPAR enhancement
• Enhanced CPU and availability management for zManager environments
• GDPS automated multisite recovery for zBX
• Continued support to help rapidly address service disruptions with IBM System z Advanced Workload Analysis Reporter (IBM zAware)
• Compression acceleration with the zEDC Express feature
• Reduced latency and lower CPU overhead with the 10GbE RoCE Express feature
• Enhanced cryptographic support of the Common Cryptographic Architecture and the IBM zEnterprise Public-Key Cryptography Standards
• Enhanced Trusted Key Entry workstation support with new functions for ease of use and continued industry compliance
• Improved resilience and performance for coupling environments with a new level of Coupling Facility Control Code (Level 19) for exploitation of Coupling Thin Interrupts

zBC12 6-Core Chip Details

The zBC12 PU chip is an evolution of the IBM zEnterprise 114 (z114) core design, and uses the following improvements:

• CMOS 13S technology
• Out-of-order (OOO) instruction processing
• Higher clock frequency
• Larger caches

Compute-intensive workloads can achieve additional performance improvements through higher clock frequency, larger caches, and compiler enhancements to provide applications the benefit of the new execution units.

Each PU chip has up to six cores running at 4.2 GHz. The PU chips come in two versions, having four active cores or five active cores.

Each PU chip has 2.75 billion transistors. Each one of the six cores has its own L1 with 64 kilobytes (KB) for instructions and 96 KB for data. Next to each core there is its private L2 cache, with 1 MB for instructions and 1 MB for data.

There is one 24 MB L3 cache. The L3 cache is a store-in shared cache across all six cores in the PU chip. It has 96 x 512 KB enhanced dynamic random access memory (eDRAM) macros, dual address-sliced and dual store pipe support, an integrated on-chip coherency manager, cache, and cross-bar switch.The L3 directory filters queries from local L4. Both L3 slices can deliver up to 160 Gbps bandwidth to each core simultaneously. The L3 cache interconnects the six cores, GX I/O buses, and memory controllers (MCs) with SC chips.

Inside the IBM zBC12 2828