Technical Overview

With the IBM zEnterprise System, IBM took smarter computing and optimized systems to a new level. For the first time it was possible to deploy an integrated hardware platform that brings mainframe and distributed technologies together, a system that can start to replace individual islands of computing and that can work to reduce complexity, improve security, and bring applications closer to the data they need. zEnterprise represents the next generation of smarter computing – hybrid computing where hundreds of workloads can run across multiple hardware platforms, all as part of a single integrated system.

IBM is introducing the IBM zEnterprise 114 (z114), the newest member of the zEnteprise family, bringing the unique value of hybrid computing to a much broader set of businesses. The z114 offers a smaller mainframe footprint and lower entry cost than the zEnterprise 196 (z196) and continues to deliver world-class secure data serving and transaction processing capabilities as well as the ability to help collapse and simplify infrastructures and efficiently host private enterprise clouds. The z114 delivers the scalability, flexibility, and performance you need at a lower capacity and attractive entry price point for your business.

Its hybrid capabilities are designed to address the complexity and inefficiency in today’s multiarchitecture data centers. As a true “system of systems,” the z114 extends the strengths and capabilities of the mainframe such as virtualization, security, fault tolerance, efficiency, and dynamic resource allocation to integrate and manage multi-tier applications running across z/OS, Linux on System z, VSE, z/VM, AIX, and Linux on System x operating environments, fundamentally changing the way data centers can be managed.

With a total systems approach designed to deploy innovative technologies, IBM System z introduces the z114, supporting zEnterprise, and offering the highest levels of reliability, availability, scalability, clustering, and virtualization. The z114 just-in-time deployment of capacity allows improved flexibility and administration, and the ability to enable changes as they happen. The expanded scalability on the z114 facilitates growth and large-scale consolidation.

The IBM zEnterprise 114 is designed to provide:

• Server improvements
  • One to two drawers (system boards)
  • Seven PUs per drawer
  • Up to 30 logical partitions
  • Up to 248 GB per partition
• Memory
  • Up to 248 GB memory (Model M10)
  • 8 GB system minimum
  • Increments of 8 or 32 GB
  • 8 GB HSA, separately managed
  • RAIM standard
• I/O
  • Zero to two I/O drawers with concurrent add/repair capability
  • Zero to two PCIe I/O drawers with concurrent add/repair capability
• Coupling
  • HCA3-O 12x optical 2 port
  • HCA3-O LR 1x optical 4 port
  • Up to 48 ISC-3 links
  • Up to 16 12x PSIFB ports (Model M10)
  • Up to 32 1x PSIFB ports (Model M10)
• zBX support
  • zManager
  • BladeCenter H (1-8 chassis) Ethernet attachment
  • Support for IBM Smart Analytics Optimizer, DataPower IX50z, System p blades, and System x blades

z114 14-Core Chip Details

The z114 PU chip is an evolution of the System z10 core design, using 12S technology, out-of-order instruction processing, higher clock frequency, and larger caches. Compute-intensive workloads can achieve additional performance improvements through higher clock frequency, larger caches, and compiler enhancements to allow applications the benefit of the new execution units. Each PU chip has up to four cores running at 3.8 GHz. The PU chips come in two versions, having three active cores or all four active cores.

The z114 server implements a four-level cache structure. Each core has its own 192 KB cache Level 1 (L1), which is split into 128 KB for data (D-cache) and 64 KB for instructions (I-cache). The L1 cache is designed as a store-through cache, meaning that altered data is also stored to the next level of memory. The next level is the private cache Level 2 (L2) that is located on each core, having 1.5 MB and also designed as a store-through cache. The cache Level 3 (L3) is also located on the PU chip and shared by the four cores, having 24 MB and designed as a store-in cache.

Cache levels L2 and L3 are implemented on the PU chip to reduce the latency between the processor and the large cache Level 4 (L4), which is located on the SC chip. Each SC chip has 96 MB, which is shared by both PUs on the processor drawer. The L4 cache uses a store-in design.

Inside the IBM Z114 2818