Technical Overview

The z10 BC further extends the leadership of System z by delivering expanded granularity and optimized scalability for growth, enriched virtualization technology for consolidation of distributed workloads, improved availability and security to help increase business resiliency, and just-in-time management of resources. The z10 BC is at the core of the enhanced System z platform and is the new face of System z.

In the area of server availability, enhancements have been engineered into the z10 BC to help eliminate unwanted down time. For example, preplanning requirements are minimized by delivering a fixed, reserved Hardware System Area (HSA) that enables dynamic creation of logical partitions, including logical channel subsystems, subchannel sets, and devices, using dynamic I/O without preplanning. Additionally, new capabilities are intended to allow you to dynamically change logical processor definitions and cryptographic co-processor definitions for a logical partition without requiring the logical partition to be deactivated and re-activated.

Further improvement to availability and flexibility is achieved with just-in-time deployment of capacity resources designed to dynamically change capacity when business requirements change. You are no longer limited by one offering configuration; instead one or more flexible configurations can be defined that can be used to solve multiple temporary situations. You can choose from multiple configurations and the configurations themselves are flexible so you can activate only what is needed from your defined configuration. Another significant change is the ability to add permanent capacity to the server when you are in a temporary state. These z10 BC enhancements are designed to allow you to take advantage of the technology helping to provide on-demand capacity more effectively. There are new terms governing System z Capacity Back Up (CBU) now available which allow customers to execute production workload on a CBU Upgrade during a CBU Test.

The IBM System z10 Business Class – A total systems approach to deliver leadership in enterprise computing: With a total systems approach designed to deploy innovative technologies, IBM System z introduces the z10 BC, supporting z/Architecture, and offering the highest levels of reliability, availability, scalability, clustering, and virtualization. The z10 BC just-in-time deployment of capacity allows improved flexibility and administration, and the ability to enable changes as they happen. The expanded scalability on the z10 BC facilitates growth and large-scale consolidation. The z10 BC is designed to provide:

• Uniprocessor performance up to 1.4 times the uniprocessor performance of the z9 BC S07 Z01 (based on LSPR mixed workload average).
• Up to 1.5 times the total system capacity for general purpose processing, of the z9 BC
• Up to 12 Processor Units (PUs) including SAPs, as compared to a maximum of 8 on the z9 BC (including SAPs)
• Up to 1.9 times as much total server available memory as a z9 BC – up to 120 gigabytes of total memory
• Up to 3.8 times as much total server available memory as a z9 BC by June 30, 2009 – up to 248 gigabytes of total memory
• Up to 78% more subcapacity choices as compared to z9 BC
• Increased host base bandwidth using InfiniBand at 6 GBps
• Hardware support for HiperDispatch
• Hardware Decimal Floating Point unit for improved numeric processing performance
• Large page support (1 megabyte pages)
• Up to 128 FICON channels
• High Performance FICON for System z (zHPF) provides improvement in performance and RAS on both FICON Express4 and FICON Express2 features
• Platform and name server registration in FICON channel
• Extended-distance FICON – helps avoid degradation of performance at extended distances
• FCP – increased performance for small block sizes
• SCSI Initial Program Load (IPL) – now a base function
• Performance improvements with HiperSockets Multiple Write Facility
• 12x DDR Coupling with InfiniBand for improved distance compared to ICB-4 links and potential cost saving by ISC-3 link consolidation
• 1x DDR Coupling over InfiniBand links supporting 10 km unrepeated distance
• STP time accuracy, availability and system management improvements
• Improved Advanced Encryption Standard (AES) 192 and 256 and stronger hash algorithms with Secure Hash Algorithm (SHA) 384 and 512
• Reduction in the availability impact of preplanning requirements
  • Fixed Hardware System Area (HSA) designed so the maximum configuration capabilities can be exploited
  • Designed to reduce the number of planned Power-on-Resets
  • Designed to allow dynamic add/remove of a new logical partition (LPAR) to new or existing logical channel subsystem (LCSS)
• Open Systems Adapter-Express3 (OSA-Express3) 10 Gigabit Ethernet with double the port density and improved performance
• Energy efficiency displays on System Activity Display (SAD) screens
• Just-in-time deployment of capacity for faster activation without dependency or referral to IBM
• Store System Information (STSI) change to support billing methodologies
• Temporary offering Capacity for Planned Event (CPE) available to manage system migrations, data center moves, maintenance activities, and similar situations
• Improved performance management with Capacity Provisioning
• Plan ahead memory that allows for non disruptive memory increases
• Support for the IBM Systems Director Active Energy Manager (AEM) for Linux on System z

z10 BC 4-Core Chip Details

Each processing unit (PU) chip is a four-core (quad-core) chip. Each of the four PU SCMs contains one PU chip. Three of the four cores (PUs) are active, making 12 PUs available on the z10 BC. Two of the 12 PUs are designated SAPs. The remaining 10 PUs may be characterized for customer use. No designated spares are available.

The L2 cache interface (L2 Intf) is shared by all four cores. The memory controller (MC) function controls access to memory. GX indicates the I/O bus controller that controls the interface to the host channel adapters accessing the I/O. The chip controls traffic between the microprocessors (cores), memory, I/O, and the L2 cache on the SC chips.

Each core on the chip runs at a cycle time of 0.286 nanoseconds (3.5 GHz). Each quad-core PU chip measures 21.97 x 21.17 mm, contains 6 km of wire, features 1188 signal and 8765 I/O connections, and has close to one billion (994 million) transistors.

Each PU has a 192 KB on-chip Level 1 cache (L1) that is split into a 64 KB L1 cache for instructions (I-cache) and a 128 KB L1 cache for data (D-cache). A second level on chip cache, the L1.5 cache, has a size of 3 MB per PU. The two levels on chip cache structure are necessary to optimize performance so that it is tuned to the high-frequency properties of each of the microprocessors (cores).

Inside the IBM z10 BC 2098